Chip design startup Verkor.io says its agentic AI system, Design Conductor, autonomously designed a complete RISC-V CPU core in 12 hours. The design started from a 219-word requirements document, and the system created a verified, layout-ready GDSII file with no human intervention during the actual design process. Verkor describes the speedup as "orders of magnitude" faster than the industry norm. A research paper backing the claims was published in March 2026, and VerCore is being positioned as the first complete RISC-V CPU core designed end-to-end by an AI agent. The chip has not been physically fabricated.
VerCore runs a 5-stage pipelined architecture with single-issue, in-order execution. It supports the RV32I and ZMMUL instruction sets, though compressed instruction support is missing. It clocked 1.48 GHz against a 1.6 GHz target and posted a CoreMark score of 3,261, roughly the level of a mid-2011 Intel Celeron SU2300. Verkor says VerCore hits a Cycles Per Instruction target of 1.5 or below and can run a uCLinux variant in simulation.
Design Conductor orchestrates large language models through a structured sequence of steps that mirrors how human engineers approach chip design, moving from RTL specification through to layout generation. Everything is produced autonomously, and the system stays compatible with existing Electronic Design Automation tools. It works well only when the input spec is written in what Verkor calls an "extremely deliberate, tight, and verifiable/measurable manner."
All verification has happened in simulation, using the Spike reference simulator and an academic ASAP7 process design kit rather than a production node. Verkor's researchers acknowledge that Design Conductor can underestimate the complexity of certain design challenges and occasionally gets stuck in debugging loops. When it could not meet timing requirements, it chose a major pipeline deepening instead of simpler, more surgical fixes. Compute requirements grow non-linearly as design complexity increases, and Verkor estimates that 5 to 10 human experts are still needed to steer the system toward production-ready results.
Verkor plans to open-source VerCore's RTL source code and build scripts by the end of April 2026, with an FPGA implementation to be showcased at the upcoming Design Automation Conference. Longer term, Verkor aims to partner with fabless companies to deploy Design Conductor as a time-to-market accelerator.