Verkor claims its AI agent designed a chip from scratch

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Verkor claims its AI agent designed a chip from scratch

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Verkor.io, a chip design startup, claims its agentic AI system called Design Conductor autonomously designed a complete RISC-V CPU core — named VerCore — in 12 hours flat. The design started from a 219-word requirements document and the system produced a verified, layout-ready GDSII file with zero human intervention during the actual design process. Verkor describes the speedup as "orders of magnitude" faster than the industry norm, and the claims are backed by a research paper published in March 2026. VerCore is positioned as the first complete RISC-V CPU core designed end-to-end by an AI agent. The important caveat is that the chip hasn't actually been physically fabricated. Under the hood, VerCore runs a 5-stage pipelined architecture with single-issue, in-order execution. It supports the RV32I and ZMMUL instruction sets, though compressed instruction support is missing. Performance-wise, VerCore clocked in at 1.48 GHz — just shy of the 1.6 GHz target — and posted a CoreMark score of 3,261, putting it roughly in the same neighborhood as a mid-2011 Intel Celeron SU2300. The design hits a Cycles Per Instruction target of 1.5 or below, and Verkor claims it can run a uCLinux variant in simulation. The Design Conductor workflow orchestrates large language models through a structured sequence of steps that mirrors how human engineers approach chip design, moving from RTL specification all the way through to layout generation. Everything is produced autonomously, and the system stays compatible with existing Electronic Design Automation tools. The system only works well when the input spec is written in what Verkor calls an "extremely deliberate, tight, and verifiable/measurable manner." The 219-word spec that kicked off VerCore wasn't some casually tossed-off prompt — it was a carefully engineered requirements document. Verification has all happened in simulation, using the Spike reference simulator and an academic ASAP7 process design kit rather than a production node. Verkor's own researchers have been candid about limitations: Design Conductor can underestimate the complexity of certain design challenges and occasionally gets stuck in debugging loops. When the system couldn't meet timing requirements, it went for a major pipeline deepening instead of applying simpler, more surgical fixes. Compute requirements grow non-linearly as design complexity increases, creating practical ceilings. Despite the "autonomous" framing, Verkor estimates 5 to 10 human experts are still needed to steer the system toward production-grade quality. On the roadmap: Verkor plans to open-source VerCore's RTL source code and build scripts by the end of April 2026, with an FPGA implementation to be showcased at the upcoming Design Automation Conference. Longer term, Verkor aims to partner with fabless companies to deploy Design Conductor as a time-to-market accelerator.